1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a dynamic random access memory (generally referred to as "DRAM") containing semiconductor devices such as a plurality of MOS field effect transistors (hereinafter referred to as "MOS transistors" or "MOS FETs").
In order to achieve a higher DRAM storage capacity, a DRAM having a configuration in which a plurality of one-transistor/one-capacitor type memory cells, each including one nMOS transistor and one capacitor, are formed on a chip has been used in recent years. When nMOS transistors (n-channel MOS type field effect transistors) are used for cell transistors for writing data to the memory cells or for bit line transfer transistors for reading out the data from these memory cells by a shared type sense amplifier, so as to attain a higher integration storage capacity of a semiconductor integrated circuit comprising the DRAM, etc., an influence of a threshold voltage between a gate and a source of each nMOS transistor must be taken into consideration.
To eliminate the influence of the threshold voltage of the nMOS transistors and to carry out stable write and read operations to and from a plurality of memory cells inside the DRAM, a step-up voltage which is higher, by at least the threshold voltage, than a source of each nMOS transistor used as a cell transistor and a bit line transfer transistor (i.e., a step-up voltage which is higher, by at least the threshold voltage, than a high voltage level of each bit line) is generated, and is supplied to the gate voltage of the nMOS transistor.
2. Description of the Related Art
To begin with, constructions of gate voltage generating portions of cell transistors and bit line transfer transistors in conventional DRAMs and their operations will be explained with reference to the accompanying drawings (FIGS. 1 to 3), in order to clarify the problems which may occur when the step-up voltage is generated so as to stably carry out write and read operations to and from a plurality of memory cells in the DRAM constituting a semiconductor integrated circuit.
FIG. 1 is a block diagram showing a construction of a cell transistor in a conventional DRAM; FIG. 2 is a block circuit diagram showing a construction of a bit line transfer transistor in the DRAM described above; and FIG. 3 is a diagram showing an operation voltage waveform at the time of read operation of cell data in the DRAM described above. Here, a gate voltage generating portion of cell transistors inside the memory cell block (i.e., memory cell array) containing a plurality of memory cells, a gate voltage generating portions of bit line transfer transistors, etc., will be referred to as a "core circuit portion" for distinguishing them from peripheral circuits inside the semiconductor integrated circuit. (The term "core circuit portion" designates a circuit portion for selecting and activating specified memory cells inside the memory cell block, and is sometimes referred to as a "memory cell driving/control portion".)
As shown in FIG. 1, each of the one-transistor/one-capacitor type memory cells of the DRAM widely used at present is constituted by a cell transistor Tc including one nMOS transistor and one cell capacitor Cc. When data "1" or "0" is written to this type of memory cell through a bit line BL, the cell transistor Tc must be activated (turned ON) by supplying an output voltage of a high voltage level to the cell transistor Tc from a word decoder unit 9 connected to a word line WL. Further, in order to conduct the data read operation from the memory cell without error by increasing the change of the voltage generated by accumulated charges Qs in the cell capacitor Cc, an input voltage which is sufficiently high to guarantee a stable operation of the cell transistor Tc must be applied to the gate.
In this case, however, the change of the voltage of the accumulated charges Qs becomes smaller than an expected value by the threshold voltage Vth between the gate and the source of the cell transistor as shown in the operation voltage waveform diagram of FIG. 3. To eliminate an influence of this threshold voltage Vth, too, a step-up voltage SVii (see FIG. 1), which is higher, by at least the threshold voltage described above, than the voltage of the source or the voltage of the drain of the nMOS transistor is supplied to the word line WL by using a step-up power source.
On the other hand, when data is read out from either one of two pairs of bit lines BLX(n), BLZ(n) and BLX(n+1), BLZ(n+1) by a shared type sense amplifier 77 (note that the sense amplifier 77 uses a reference power source voltage Vii) as shown in FIG. 2, either one of read transistors Tx(n), Tz(n) and read transistors Tx(n+1), Tz(n+1) corresponding to either one of the two pairs of the bit lines must be activated (turned ON) by either one of the bit line transfer signals BLTX(n) and BLTX(n+1) of the step-up voltage level that are output from bit line transfer signal generating units 70-n and 70-n+1, respectively. Further, to guarantee a stable operation of the sense amplifier 77, each of the bit line transfer signals represented as BLTX must have a voltage level which is sufficiently high.
However, in order to carry out the read operation of data without error by eliminating the influence of the threshold voltage Vth, the bit line transfer signals BLTX having an output level of the step-up voltage, which is higher, by at least the threshold voltage described above, than the voltage of the source or the voltage of the drain of the nMOS transistor, is also supplied to the bit line transfer signal generating units 70 (70-n and 70-n+1) by using a step-up power source generating a step-up voltage SVii (see FIG. 2).
FIG. 4 is a block circuit diagram showing a state in which a step-up voltage is used in a semiconductor integrated circuit according to the prior art, and FIG. 5 is an operation voltage waveform diagram showing the relationship between a step-up voltage and a circuit selecting signal in a semiconductor integrated circuit according to the prior art. The construction of the semiconductor integrated circuit comprising the DRAM according to the prior art, and its operation, will be hereby explained exemplarily. Incidentally, like reference numerals will be hereinafter used to identify like constituent elements used in FIGS. 4 to 7.
In the semiconductor integrated circuit according to the prior art shown in FIG. 4, a step-up voltage generating unit 5 inside a chip generates the step-up voltage (drive voltage) SVii higher, by at least the threshold voltage, than the voltage of the source or the voltage of the drain of the nMOS transistor, and supplies this voltage to a core circuit portion (memory cell block drive/control portion) 3 as the step-up power source of the core circuit portion 3 inclusive of the word decoder unit 9 and the bit line transfer signal generating unit 70.
An explanation will be given on this point in further detail. When the memory cell block inside the semiconductor integrated circuit has a plurality of operation blocks and when the data is written to a specified memory cell inside one memory cell block, the output level of the bit line transfer signal BLTX for selecting the operation block containing this specified memory cell is set to the voltage level of a source voltage Vss (that is, a low voltage level) while the step-up voltage SVii is supplied to the specified memory cell so as to selectively activate this memory cell and to change the output voltage of the cell transistors inside the memory cell, as shown in the operation waveform diagram of FIG. 5.
As described above, in order to eliminate the influence of the threshold voltage of the nMOS transistors and to stably carry out write and read operations to and from a plurality of memory cells inside the DRAM in the conventional semiconductor integrated circuit, the step-up voltage SVii higher by at least the threshold voltage than the voltage of the source or the voltage of the drain of the nMOS transistors is generated and is supplied to the gate voltage of the nMOS transistors of the word decoder unit, the bit line transfer signal generating unit, and so forth.
Next, the problems encountered when the memory cells inside the semiconductor integrated circuit are operated by using the step-up voltage as described above will be explained with reference to the accompanying drawings (FIGS. 6 and 7).
FIG. 6 is a graph showing the relationship between the power source voltage of the MOS transistor and an inter-band tunnel current, and FIG. 7 shows the mode of an increase in a stand-by current in the prior art.
Generally speaking, the word decoder unit and the bit line transfer signal generating unit of the cell array containing the memory cells and the cell drive/control portion are inclined to include a relatively large number of circuits. Further, because the step-up voltage SVii higher than the voltage of the reference power source is used as the power source for circuits constituting the word decoder unit, etc., the step-up voltage described above is always applied to the MOS transistors of an input portion of the word decoder unit, etc., even under the stand-by state in which the memory cells are not selected. As shown in FIG. 6, a stand-by current Icc2 increases due to the influence of the inter-band tunnel current as the power source voltage of the MOS transistor becomes higher. Particularly when the power source voltage reaches a certain high voltage, the stand-by current is likely to increase drastically.
It will be hereby assumed, for example, that when the step-up voltage is 4.5V, a stand-by current of 50 fA (50.times.10.sup.-15 A) per .mu.m gate width (10.sup.-6 m) of the MOS transistor flows as an inter-band tunnel current (inter-band leakage current). Assuming that the total gate width of the MOS transistors in the cell array to which the step-up voltage is applied at this time is W (.mu.m) and an efficiency of the circuit of the step-up voltage generating unit is 25%, the increment of the stand-by current brought about due to the inter-band tunnel current can be expressed by the following formula: EQU .DELTA.Icc2=(50fA.times.W .mu.m).times.4
Assuming hereby that the inter-band tunnel current is the same at the integrated storage capacity of the three generations with each other (that is, integrated storage capacity of 64 Mbits, 256 Mbits and 1 Gbit) and that the total gate width of the MOS transistors in the cell array to which the step-up voltage is applied shifts as tabulated in the following Table 1, the increment of the stand-by current brought about due to the influences of the inter-band tunnel current can be expressed as in FIG. 7.
TABLE 1 ______________________________________ Total Gate Width versus Integrated Storage Capacity ______________________________________ Integrated Storage 64 M 256 M 1 G Capacity (bit) Total Gate Width 125 .times. 10.sup.4 250 .times. 10.sup.4 500 .times. 10.sup.4 (.mu.m) ______________________________________
As is obvious from FIG. 7, the influence of the increment of the stand-by current brought about due to the influence of the inter-band tunnel current reaches the level that cannot be neglected when the integrated storage capacity becomes higher. In other words, as the integrated storage capacity of the semiconductor. integrated circuit becomes higher, an increase in the stand-by current resulting from the use of the step-up voltage for the word decoder unit, the bit line signal generating unit, and the like, of the cell array becomes more remarkable. Consequently, another problem occurs in that power consumption of the memory cells at the time of stand-by state increases.